11, 2009, and entitled “Cross-Coupled Transistor Layouts in Restricted Gate Level Layout Architecture,” Which claims priority under 35 USC 119(e) to US ...

... Cross- Coupled Transistors Defined by Physically Separate Gate Electrodes within Gate Electrode Level Linear Gate Level Cross-Coupled Transistor Device ...

Filing Date TELAP015AC11 Linear Gate Level Cross- Coup led Transistor Device with Complimentary Pairs of Cross- Coupled Transistors Defined by Physically ...

4 shows diffusion and gate level layouts of a cross-coupled transistor configuration, in accordance with one embodiment of the present invention.

11, 2009, and entitled “Cross-Coupled Transistor Layouts in Restricted Gate Level Layout Architecture,” which claims priority under 35 USC 119(e) to US ...

Filing Date TELAP015AC11 Linear Gate Level Cross- Coup led Transistor Device with Complimentary Pairs of Cross- Coupled Transistors Defined by Physically ...

12/402465, filed Mar. ll, 2009, and entitled “Cross-Coupled Transistor Layouts in Restricted Gate Level Layout Architecture,” which claims priority under 35 ...

Filing Date TELAP015AC12 Linear Gate Level Cross- Coup led Transistor Device with Cross-Coupled Transistors Defined on Two Gate Electrode Tracks with ...