Method of operation of a memory controller
Filed: September 25th, 2000 [Granted]
Patent Number: 6304937
... Svensson, Christer et al., "High Speed CMOS Chip to Chip Communications Circuit," IEEE International Symposium on Circuits and Systems, pp.
Memory module having signal lines configured for sequential arrival of ...
Filed: April 17th, 2009 [Granted]
Patent Number: 7870322
... US PATENT DOCUMENTS 3651432 A 3/1972 Henschen et al 333/33 3659205 A 4/1972 Cooke etal 455/198.1 3718936 A * 2/1973 Rice, Jr 347/148 3820081 A 6/1974 ...
System having a controller device, a buffer device and a plurality of memory ...
Filed: January 11th, 2008 [Granted]
Patent Number: 7523248
... FOREIGN PATENT DOCUMENTS OTHER PUBLICATIONS Rambus Inc., "8/9-Mbit (1Mx8/9) & 16/18Mbit (2Mx8/9) RDRAM — Preliminary Information," Rambus Inc. Data ...
Memory device with clock multiplier circuit
Filed: March 31st, 2005 [Granted]
Patent Number: 7209397
... FOREIGN PATENT DOCUMENTS OTHER PUBLICATIONS European Search Report and Written Opinion for EP 1 653374 A3 (Application No. 05022021.9) , Jul.
Memory device with clock multiplier circuit
Filed: March 31st, 2005 [Granted]
Patent Number: 7209397
... FOREIGN PATENT DOCUMENTS OTHER PUBLICATIONS European Search Report and Written Opinion for EP 1 653374 A3 (Application No. 05022021.9) , Jul.
Method, system and memory controller utilizing adjustable read data delay ...
Filed: January 18th, 2006 [Granted]
Patent Number: 7177998
... 714/736 FOREIGN PATENT DOCUMENTS OTHER PUBLICATIONS Samsung Electronics, SDRAM Module, Preliminary KMM377S1620CT2, Rev. 1, Nov. 1998, 12 pages.
System for a memory device having a power down mode and method
Filed: June 14th, 2005 [Granted]
Patent Number: 7581121
... Response to Non-Final Office Action, US Appl. No. 11/030382, filed on Jan. 6 , 2005, May 19, 2008. Final Office Action, United States Patent & Trademark ...
Communication system with low power, DC-balanced serial link
Filed: January 21st, 2005 [Granted]
Patent Number: 7199728
... US PATENT DOCUMENTS 370/217 345/204 OTHER PUBLICATIONS EIA/JEDEC Standard No . 8-6 (EIA/JESD8-6) "High Speed Transceiver Logic (HSTL) A 1.5 V Output ...